The present disclosure relates generally to computer processor instruction sequencing and, in particular, to a method and system for implementing store buffer resource allocation in support of variable length store data operations.
When store operations for high performance processors are issued, they require reserving resources to perform the storage operation. These resources generally consist of an address queue and a data queue. In many cases, the store data length is fixed and so the address and the data queues are reserved together. However, once the data length is no longer fixed (e.g., variable length stores), efficient allocation of store buffer resources becomes more difficult to manage.
One solution is to calculate the length of the data field at address generation time and reject the data if there are insufficient resources available to store it. This approach can be difficult to achieve in a high-frequency design and also requires that all buffer resources become available prior to starting the operation. Another approach is to move the allocation back to the issuing unit, such that accessing the data requires the allocation of a buffer tag. This approach allows for partial data to get through before resources are available, but does not allow for more intelligent buffer allocation, which may be aligned by memory address. This scheme has a higher latency due to the distance of the allocation to the releasing logic.
What is needed, therefore, is a buffer allocation scheme that can handle multiple data for each address queue allocated and can also allocate data buffers based on the destination of the store data.